Some CMOS (Complementary Metal-Oxide Semiconductor) (devices incorporate MOSFET's (Metal-Oxide-Semiconductor Field-Effect Transistors) to alternatively sample an AC input signal and a DC reference signal onto a common load. In such applications as switched-capacitor filters, auto-zeroed comparators and amplifiers, and analog-to-digital convertors, among others, a MOSFET switching transistor is provided in the DC input signal path and another MOSFET switching transistor is provided in the AC input signal path. The MOSFET switching transistor in the DC input signal path is switched in non-overlapping phase opposition to the MOSFET switching transistor provided in the AC input signal path in such a way as to controllably switch the DC input signal and the AC input signal alternatively to the same load. As a result of parasitic capacitances between both the gate to source and gate to drain terminals of the MOSFET switching transistor in the DC input signal path as well as charge in the source to drain channel of the MOSFET switching transistor in the DC input signal path, undesirable currents are produced as the MOSFET switching transistor in the DC input signal path is switched from its "on" to its "off" condition. The currents induced by the parasitic capacitances and channel charge corrupt the DC input signal sampled onto the load, placing thereby a limit on the accuracy with which the AC signal is able to be alternatively sampled to the same load.
To compensate the switching MOSFET in the DC input signal path for the unwanted currents, so-called "charge feedthrough error", it is known to provide a second, compensating MOSFET in the DC input signal path in series relation with the switching MOSFET thereof. The capacitance of the second, compensating MOSFET is selected to be equal to the parasitic capacitance exhibited by the gate to drain terminals of the MOSFET switching transistor in the DC input signal path to be compensated. The second, compensating MOSFET, switched in phase opposition to the MOSFET switching transistor to be compensated in the DC input signal path, produces a current of a sign that cancels out the charge feedthrough error of the MOSFET switching transistor to be compensated in the DC input signal path. So much as the magnitude of the unwanted currents attributable to both the gate to source parasitic capacitance and to the channel charge are negligible with respect to the unwanted current attributable to the gate to drain parasitic capacitance of the switching MOSFET to be compensated, just so much does the compensating MOSFET of the heretofore known charge feedthrough error compensation technique provide cancellation of the charge feedthrough error. But in many if not all practicable embodiments, the unwanted current attributable to the charge of the channel and the unwanted current attributable to the parasitic capacitance of the gate to source terminals of the MOSFET switching transistor to be compensated are often either commensurate with or greater than the current attributable to the parasitic capacitance of the gate to drain parasitic capacitance thereof, which currents, uncompensated by the heretofore known charge feedthrough error compensation technique, corrupt the sampling of the DC input signal to the load and thereby limit the accuracy with which the AC input signal is able to be sampled to the same load.
Other accuracy limiting factors in addition to the failure of the heretofore known charge feedthrough error compensation technique to cancel the unwanted currents attributable both to the channel charge and to the gate to source parasitic capacitance of the switching MOSFET in the DC input signal path are the electrical asymmetries that belong to the switching and compensating MOSFET transistors as they are switched in phase-opposition between their "on" and "off" conditions. Not only is the "on" capacitance not the same in magnitude as the "off" capacitance of the several transistors, so that the unwanted current attributable to the magnitude of the gate to drain parasitic capacitance of the switching MOSFET to be compensated really is not and cannot be precisely matched by the current attributable to the magnitude of the parasitic capacitance of the compensating MOSFET as the former is turned "off" and the latter "on", not only is the range of potential swing from the turn-off voltage to the off potential as one MOSFET is being turned to its "off" condition not the same in magnitude as the voltage swing from the turn-off voltage to the on potential of the other MOSFET as it is being turned to its "on" condition, so that the self-cancelling currents, due to the variation in the magnitude of the voltage swing across the parasitic capacitances of the phase-opposed switching and compensating MOSFETS, are not and cannot be precisely matched, but also it is practicably impossible to provide precisely-synchronized phase-opposed (or other relative phase) clocking signals. In addition, the phase-opposed switching of the switching and compensating MOSFETS gives rise to the asymmetry that the compensating MOSFET produces its cancelling current before the switching MOSFET to be compensated is fully in its "off" condition. The compensating current produced by the compensating MOSFET, instead of cancelling the charge feedthrough error by flowing to the load, rather flows out along the DC input signal path in such a way as to be dissipated by the input impedance thereof. While it is known that a phase delay may be interposed by which the switching and compensating MOSFETS are alternatively switched with an interval sufficient to enable the switching MOSFET to be fully turned to its "off" condition before the compensating MOSFET is turned to its "on" condition, the magnitude of the charge feedthrough error can nonetheless remain unsatisfactorily large.